1. Field of the Invention
The present invention relates to a MOS stage with high output resistance, particularly for integrated circuits.
2. Prior Art
A stage with high output resistance is often useful in the manufacture of integrated circuits, for example to provide an amplifier stage with a high voltage gain value. An example of a known stage with high output resistance in widespread use to achieve a high voltage gain, is found in the "cascode" stage described for example in P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, published by Holt, Rinehart and Winston, 1987, ISBN 0-03-006587-9, pages 282-283).
A cascode stage of this type is illustrated in FIG. 1, wherein M1' and M2' are two N-channel MOS enhancement transistors; M3' and M4' are two P-channel MOS enhancement transistors; V.sub.DD is a positive supply voltage; V.sub.REF1 and V.sub.REF2 are two fixed voltages. The transistor M1' is the input transistor, and the input voltage signal V.sub.IN is applied to its gate electrode; the node between the transistors M2' and M3' is the output terminal OUT. The gate electrode of the transistor M4', connected to terminal A in FIG. 1, is often connected to a fixed bias voltage V.sub.RIAS which determines the value of the direct current flowing across the stage. As an alternative it can be connected to a voltage which is not fixed but "repeats" the input signal voltage V.sub.IN, shifting its direct current value to an appropriate level (i.e. to the value required to correctly bias the stage). This second solution allows to obtain a higher overall voltage gain of the stage, since in practice it uses both the transistor M1' and the transistor M4' as input elements for the stage.
The output resistance of the above described stage is obviously equal to the parallel of the resistances opposed by the two paths which connect the output terminal OUT respectively to the power supply and to the ground. As can be calculated (see P. R. Gray and R. W. Meyer, Analysis and Design of Analog Integrated Circuits, published by John Wiley and Sons, 2nd edition, 1984, ISBN 0-471-87493-0, pages 711-714, or the previously mentioned book by Allen and Holberg, page 297) ignoring the terms due to the body effect for the sake of simplicity, these two resistances are respectively equal to EQU r.sub.o3 (1+g.sub.m3 r.sub.o1)+r.sub.o4,
and EQU r.sub.o2 (1+g.sub.m2 r.sub.o1)+r.sub.o4,
where r.sub.o1 is the output resistance of the i-th transistor (Mi) and g.sub.m1 is its respective transconductance. By first approximation (g.sub.m1 r.sub.o1 &gt;&gt;1), these resistances are substantially equal to r.sub.o3 r.sub.o4 g.sub.m3 and r.sub.o2 r.sub.o1 gm.sub.m2.
The advantage of the cascode stage is immediately apparent by observing that the resistance opposed by each of the two paths (which, in the absence of the cascode structure, would be equal to the output resistance r.sub.o1 of the single transistor M4' or M1' present on said path) is multiplied by the factor g.sub.m1 r.sub.o1 of the added transistor (M3' or M2').
As is known, for the correct operation of the amplifier stage all the transistors M1', . . . , M4' must operate in their saturation region. The output voltage of the cascode stage can thus assume, as maximum and minimum values respectively, approximately V.sub.REF2 +.vertline.V.sub.th.p .vertline., and V.sub.REF1 -V.sub.th.n, where V.sub.th.p and V.sub.th.n respectively constitute the threshold voltages of the P-channel and N-channel transistors. Output voltage values V.sub.OUT beyond the interval defined by the indicated limits are incorrect, since in this case the transistor M2' (for values of V.sub.OUT lower than V.sub.REF1 -V.sub.th.n) or the transistor M3' (for values of V.sub.OUT higher than V.sub.REF2 +.vertline.V.sub.th.p .vertline.) would no longer operate in their saturation region. The output dynamics of the stage is this equal to V.sub.REF2 -V.sub.REF1 +.vertline.V.sub.th.p .vertline.+V.sub.th.n.
Naturally V.sub.REF1 and V.sub.REF2 are such that the two transistors M1' and M4' also operate always in their saturation region: in other words, the absolute value of the voltage V.sub.DS occurring between the drain electrode and the source electrode of each of said two transistors is always higher than .vertline.V.sub.DSsat .vertline., where V.sub.DSsat indicates the minimum modulus value of the voltage between the drain and the source of a saturated transistor (which naturally depends on the bias conditions of the transistor, in particular on the current flowing through it). To conclude, V.sub.DSsat is the minimum voltage between the drain and the source of a transistor which ensures that said transistor, under those bias conditions, is saturated. This voltage is termed hereafter transistor saturation drain-source voltage.
If an output dynamics equal to V.sub.th.n +.vertline.V.sub.th.p .vertline. is sufficient, the gate electrodes of the two transistors M2' and M3' can be connected to the same fixed voltage V.sub.REF (in this case, naturally, the interval of values allowed for the output voltage of the stage is delimited by the values V.sub.REF -V.sub.th.n and V.sub.REF +.vertline.V.sub.th.p .vertline.).
A disadvantage of the cascode stage resides in the fact that it is necessary to generate the two voltages V.sub.REF1 and V.sub.REF2 (these voltages being preferably generated internally to the integrated circuit in which the amplifier stage is included) and that it is necessary to have interconnection lines to transfer the two voltages V.sub.REF1 and V.sub.REF2 from the location where said voltages are generated (or from the pins at which they are applied to the circuit) to the gate electrodes of the two transistors M2' and M3'. This, besides entailing difficulties during design, also occupies silicon area and complicates the layout of the integrated circuit.
This disadvantage is reduced, but not eliminated, if a single reference voltage V.sub.REF is used; this, however, is not always possible.
Long interconnection lines can naturally be avoided by generating the voltages V.sub.REF1 and V.sub.REF2 on-the-spot at all the points of the circuit where they are required, but this, too, causes the disadvantage of occupying silicon area and dissipates power.
The folded cascode stage (see the aforementioned book by Allen and Holberg, pages 421-426, FIGS. 8.4-12 onwards: or the article by P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design--A Tutorial Overview, published in IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, December 1982, pages 977-978 and FIG. 18) is an output stage structure which is based on the same concept described above and improves some of its operating characteristics. This structure, however, is more complicated than the simple cascode, and does not avoid the need for the two reference voltages V.sub.REF1 and V.sub.REF2.